Some conventional Ethernet network systems support optional Forward Error Correction (FEC) protocols as an additional measure of packet integrity, which may be useful on channels having marginal quality. FEC protocols are processor intensive, and enabling FEC protocols typically degrades system performance and increases latency and the overall power demand of a network node. In the conventional Ethernet approach, a node's receiver may choose to leave the FEC decoder off until channel quality is sufficiently poor that the decoder must be enabled or leave the FEC decoder on until the channel quality is sufficiently good. The change in latency overhead associated with the enablement or disablement of a FEC decoding scheme is not accounted for when synchronizing precision clocks between node elements. Thus, clock synchronization may become impossible, or at least, beyond tolerable limits for certain applications that require very precise clock synchronization.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.